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semiconductor group 1 type ordering code package sda 3302-5 q67000-h5112 p-dip-18-5 sda 3302-5x q67000-h5111 p-dso-20-1 (smd) sda 3302-5x6 q67000-h5110 p-dso-16-1 (smd) sda 3302-5x q67006-h5111 p-dso-20-1 tape & reel (smd) sda 3302-5x6 q67006-h5110 p-dso-16-1 tape & reel (smd) 02.97 ghz pll with i 2 c bus and four chip addresses sda 3302 family bipolar ic preliminary data features l 1-chip system for mpu control (i 2 c bus) l 4 programmable chip addresses l short pull-in time for quick channel switch-over and optimized loop stability l charge pump output with switch off option l up to 3*) high current band switch outputs (20 ma) l up to 4*) output ports (5 ma) *) depending on version p-dip-18-5 p-dso-20-1 p-dso-16-1
semiconductor group 2 functional description combined with a vco (tuner) the sda 3302 device, with four hardware-switched chip addresses, forms a digitally programmable phase-locked loop for use in television sets with pll frequency-synthesis tuning. the pll permits precise crystal-controlled setting of the frequency of the tuner oscillators between 16 and 1300 mhz in increments of 62.5 khz. the tuning process is controlled by a microprocessor via an i 2 c bus. the crystal oscillator generates a sinusoidal signal suppressing the higher-order harmonics, which reduces the moir noise considerably. circuit description tuning section (refer to block diagram) uhf/vhf the tuner signal is capacitively coupled at the uhf/vhf input and subsequently amplified. the reference input ref should be decoupled to ground using a capacitor of low series inductance. the signal passes through an asynchronous divider with a fixed ratio of p = 8, an adjustable divider with ratio n = 256 through 32767 and is then compared in a digital phase/frequency detector to a reference frequency f ref of 7.8125 khz. the latter is derived from a balanced, low-impedance 4 mhz crystal oscillator q1, q2 (pin q1, q2), whose output signal is divided by q = 512. the phase detector has two outputs up and down that drive the two current sources i + and i C of a charge pump. if the negative edge of the divided vco signal appears prior to the negative edge of the reference signal, the i + current source pulses for the duration of the phase difference. in the reverse case the i C current source pulses. pd, ud when the two signals are in phase, the charge-pump output (pd) goes high- impedance (pll is locked). an active low-pass filter integrates the current pulses to generate the tuning voltage for the vco (internal amplifier an external transistor at the ud output and an external rc circuitry). the charge-pump output can also be set to high-impedance state when control bit t0 = 1. here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuitry. ud can be disconnected internally by the control bit os to enable external adjustments. by means of a control bit 5i the pump current can be switched between two values by software. this switchover permits alteration of the control response of the pll in the locked-in state. in this way different vco gains in the different tv bands can be compensated for example. ref sda 3302 family
semiconductor group 3 circuit description (contd) p0-p2 the software-switched outputs (p0, p1, p2) can be used for direct band selection (20-ma current output). p4-p7 p4, p5, p6 and p7 are open-collector outputs for a variety of different purposes. the test bit t1 = 1 switches the test signals f ref (4 mhz/512) and cy (divided input signal) to p6 and p7. cas four different chip addresses can be set by appropriate connection of pin cas. i 2 c-bus interface scl, sda data are exchanged between the processor and the pll on the i 2 c bus. the clock is produced by the processor (input scl), while pin sda works as an input or output depending on the direction of the data (open collector; external pullup resistor). both inputs have hysteresis and a lowpass characteristic, which enhances the noise immunity of the i 2 c bus. the data from the processor are applied to an i 2 c bus controller and filed in registers according to their function. when the bus is free, both lines are in the marking state (sda, scl are high). each telegram begins with a start condition and ends with the stop condition. start condition: sda goes low while scl remains high; stop condition: sda goes high while scl remains high. all further data exchanges occur while scl is low and are accepted by the controller with the positive clock edge. for what follows, refer to the table of logic allocations. all telegrams are transmitted byte by byte, followed by a ninth clock pulse, during which the controller puts the sda line on low (acknowledge condition). the first byte consists of seven address bits, with which the processor selects the pll from a number of peripheral devices (chip select). the eighth bit is always low. in the data portion of the telegram the first bit of the first or third data byte determines whether a divider ratio or control information follows. in each case the byte following the first byte must be of the same data type (or a stop condition). v s , gnd when the supply voltage is applied, a power-on reset circuit prevents the pll from putting the sda line on low, which would block the bus. sda 3302 family
semiconductor group 4 circuit description (contd) logic allocations divider ratio n = 16384 n14 + 8192 n13 + 4096 n12 + 2048 n11 + 1024 n10 + 512 n9 + 256 n8 + + 128 n7 + 64 n6 + 32 n5 + 16 n4 + 8 n3 + 4 n2 + 2 n1 + n0 band selection p2-p0 = 1 open-collector output is active. port outputs p7-p4 = 1 open-collector output is active. pump current switchover 5i = 1 high current. ud disable os = 1 v d is disabled. test mode t1, t0 = 0,0 normal mode t1 = 1 p6 = f ref ; p7 = cy t0 = 1 tristate charge pump pd is in high-impedance. msb a = acknowledge address byte 11000ma1ma00a prog. divider byte 1 0 n14 n13 n12 n11 n10 n9 n8 a prog. divider byte 2 n7 n6 n5 n4 n3 n2 n1 n0 a control info. byte 1 1 5i t1 t0 1 1 1 os a control info. byte 2 p7 p6 p5 p4 x p2 p1 p0 a sda 3302 family
semiconductor group 5 circuit description (contd) chip-address switching pulse diagram telegram examples start-addr-dr1-dr2-cw1-cw2-stop start = start condition start-addr-cw1-cw2-dr1-dr2-stop addr = address start-addr-dr1-dr2-cw1-stop dr1 = divider ratio 1st byte start-addr-cw1-cw2-dr1-stop dr2 = divider ratio 2nd byte start-addr-dr1-dr2-stop cw1 = control word 1st byte start-addr-cw1-cw2-stop cw2 = control word 2nd byte start-addr-dr1-stop stop = stop condition ma1 ma0 voltage on cas 00 (0-0.1) v s 0 1 open 10 (0.4-0.6) v s 11 (0.9-1) v s sda 3302 family
semiconductor group 6 pin configuration (sda 3302-5) (top view) p-dip-18-5 sda 3302 family
semiconductor group 7 pin definitions and functions (sda 3302-5) pin no. symbol function 1 pd active-filter input/charge-pump output 2 q1 crystal 3 q2 crystal 4 sda data input/output for i 2 c bus 5 scl clock input for i 2 c bus 6 p7 port output (open collector) 7 p6 port output (open collector) 8 p5 port output (open collector) 9 p4 port output (open collector) 10 cas chip-address switchover 11 p2 port output (open collector) 12 p1 port output (open collector) 13 p0 port output (open collector) 14 v s supply voltage 15 uhf/vhf signal input 16 ref amplifier reference input 17 gnd ground 18 ud output active filter sda 3302 family
semiconductor group 8 pin configuration (sda 3302-5x) (top view) p-dso-20-1 sda 3302 family
semiconductor group 9 pin definitions and functions (sda 3302-5x) pin no. symbol function 1 pd active-filter input/charge-pump output 2 q1 crystal 3 q2 crystal 4 n.c. not connected 5 sda data input/output for i 2 c bus 6 scl clock input for i 2 c bus 7 p7 port output (open collector) 8 n.c. not connected 9 p6 port output (open collector) 10 p5 port output (open collector) 11 p4 port output (open collector) 12 cas chip-address switchover 13 p2 port output (open collector) 14 p1 port output (open collector) 15 p0 port output (open collector) 16 v s supply voltage 17 uhf/vhf signal input 18 ref amplifier reference input 19 gnd ground 20 ud active-filter output sda 3302 family
semiconductor group 10 pin configuration (sda 3302-5x6) (top view) p-dso-16-1 sda 3302 family
semiconductor group 11 pin definitions and functions (sda 3302-5x6) pin no. symbol function 1 pd active-filter input/output pump output 2 q1 crystal 3 q2 crystal 4 sda data input/output for i 2 c bus 5 scl clock input for i 2 c bus 6 p7 port output (open collector) 7 p6 port output (open collector) 8 p5 port output (open collector) 9 p4 port output (open collector) 10 cas chip-address switchover 11 p1 port output (open collector) 12 v s supply voltage 13 uhf/vhf signal input 14 ref amplifier reference input 15 gnd ground 16 ud output active filter sda 3302 family
semiconductor group 12 pin definitions and functions, reference list sda 3302 p-dip-18-5 pin no. sda 3302x p-dso-20-1 pin no. sda 3302x6 p-dso-16-1 pin no. symbol function 1 1 1 pd input active-filter input charge pump output 2 2 2 q1 crystal 3 3 3 q2 crystal - 4 - n.c. not connected 4 5 4 sda data input/output for i 2 c bus 5 6 5 scl clock input for i 2 c bus 6 7 6 p7 port output (open collector) - 8 - n.c. not connected 7 9 7 p6 port output (open collector) 8 10 8 p5 port output (open collector) 9 11 9 p4 port output (open collector) 10 12 10 cas chip-address switchover 11 13 - p2 port output (open collector) 12 14 11 p1 port output (open collector) 13 15 - p0 port output (open collector) 14 16 12 v s supply voltage 15 17 13 uhf/vhf signal input 16 18 14 ref amplifier reference input 17 19 15 gnd ground 18 20 16 ud output active filter sda 3302 family
semiconductor group 13 block diagram sda 3302-5 pin nos. refer to p-dip-18 package only. for other packages, see reference list on page 16 sda 3302 family
semiconductor group 14 2) pin nos. refer to p-dip-18 package absolute maximum ratings t a = 25 c parameter symbol 2) limit values unit remarks min. max. supply voltage v s C 0.3 6 v output pd v 1 C 0.3 v s v crystal q1 v 2 C 0.3 v s v crystal q2 v 3 C 0.3 v s v bus input/output sda v 4 C 0.3 6 v bus input scl v 5 C 0.3 6 v port output p7, p6, p5, p4 v 6, 7, 8, 9 C 0.3 16 v chip-address switchover v 10 C 0.3 v s v port output p2, p1, p0 v 11, 12, 13 C 0.3 16 v open collector signal input uhf/vhf v 15 C 0.3 0.3 v for v s = 0 v reference input ref v 16 C 0.3 0.3 v for v s = 0 v output active filter ud v 18 C 0.3 v s v bus output sda i 4l C 1 5 ma open collector port output p7, p6, p5, p4 i 6l, 7l, 8l, 9l C 1 5 ma open collector port output p2, p1, p0 i 11l, 12l, 13l C 1 20 ma open collector chip temperature t c 125 c total port output current z il 25 ma storage temperature t stg C 40 125 c thermal resistance (system-air) r thsa 80 k/w sda 3302 family
semiconductor group 15 absolute maximum ratings t a = 25 c parameter symbol 2) limit values unit remarks min. max. operating range supply voltage v s 4.5 5.5 v ambient temperature t a C20 80 c input frequency f 15 16 1300 mhz crystal frequency f 2, 3 4 mhz programmable divider factor n 256 32767 1) design note: no 100 % final inspection. 2) pin nos. refer to p-dip-18 package sda 3302 family
semiconductor group 16 characteristics v s = 5 v; t a =25 c parameter symbol 2) limit values unit test condition test circuit min. typ. max. current consumption i s 35 ma v s =5 v 1 crystal-oscillator frequency f 2, 3 3.99975 4.000 4.00025 mhz series capaci- tance 18 pf; f xtal = 4 mhz 1 oscillator level 1) (voltage across crystal) v 2, 3 2.6 vpp margin from 1st 1) and 2nd harmonic 20 db input sensitivity uhf/vhf a 15 a 15 a 15 C 27/10 C 27/10 C 27/10 3/315 3/315 3/315 3) f 15 = 70-500 mhz f 15 = 1000 mhz f 15 = 1100 mhz 2 2 2 band-select outputs p0-p2 (switch with open collector) reserve current i 13h 10 m a v 13h = 13.5 v 3 residual voltage v 13l 0.5 v i 13h =20ma 3 port outputs p4-p7 (switch with open collector) reserve current i 9h 10 m a v 9h = 13.5 v 4 residual voltage v 9l 0.5 v i 9l = 1.7 ma 4 note: the sum of the currents in ports p0-p7 must not exceed 25 ma phase-detector output pd pump current i 1h 90 230 300 m a5 i = high; v 1 =2 v pump current i 1h 22 50 75 m a5 i = low; v 1 =2 v output voltage v 1l 1.0 2.5 v locked 1) design note: no 100 % final inspection. 2) pin nos. refer to p-dip-18 package 3) dbm/mv rms into 50 w sda 3302 family
semiconductor group 17 output active filter ud (t0 = 1) output current C i 18 500 m a v 18 = 0.8 v; i ih =90 m a 5 output voltage v 18 100 mv v 1l =0 v 5 output voltage v 18 500 mv os = 1 5 chip-address switchover input current i 10h 50 m a v 10h =5 v 7 input current Ci 10h 50 m a v 10h =0 v 7 bus inputs scl, sda input voltage v 5h v 5l 3 5.5 5.5 v v 6 6 input current i 5h 10 m a v 5h = v s 6 input current C i 5l 20 m a v 5l =0 v 6 output sda (open collector) reverse current i 4h 10 m a v 4h = 5.5 v 6 output voltage v 4l 0.4 v i 4l =3ma 6 edges scl, sda rise time t r 1 m s6 fall time t f 0.3 m s6 shift clock scl frequency f 5 0 100 khz 6 h-pulse width t 5h 4 m s6 l-pulse width t 5l 4.7 m s6 2) pin nos. refer to p-dip-18 package characteristics (contd) v s = 5 v; t a =25 c parameter symbol 2) limit values unit test condition test circuit min. typ. max. sda 3302 family
semiconductor group 18 start setup time t susta 4.7 m s6 hold time t hdsta 4 m s6 stop setup time t susto 4.7 m s6 bus free t buf 4.7 m s6 data exchange setup time t sudat 0.25 m s6 hold time t hddat 0 m s6 input hysteresis 1) scl, sda 300 mv lowpass cutoff 1) frequency scl, sda 500 khz 1) design note: no 100 % final inspection. 2) pin nos. refer to p-dip-18 package characteristics (contd) v s = 5 v; t a =25 c parameter symbol 2) limit values unit test condition test circuit min. typ. max. sda 3302 family
semiconductor group 19 test circuit 1 sda 3302 family
semiconductor group 20 test circuit 2 test circuit 3 sda 3302 family
semiconductor group 21 test circuit 4 test circuit 5 sda 3302 family
semiconductor group 22 test circuit 6 test circuit 7 i 2 c bus timing diagram sda 3302 family
semiconductor group 23 application circuit sda 3302 family
semiconductor group 24 application circuit calculation of loop filter loop bandwidth w r = ? ( i p k vco ) / ( c 1 p n ) attenuation: x = 0.5 w r r c 1 p = prescaler n = programmable divider i p = pump current k vco = tuner slope r , c 1 = loop filter example for channel 47: p = 8, n = 11520, i p = 100 m a; k vco = 18.7 mhz/v, r = 22 k w , c 1 = 180 nf, w r = 336 hz, f r = 54 hz, x = 0.67 standard dimensioning: c 2 = c 1/5 note: the high-impedance port outputs and cas can be blocked against external noise with a capacitor of 1 nf. sda 3302 family
semiconductor group 25 input sensitivity i 2 c bus noise immunity the sinusoidal noise pulses are applied via a coupling capacitance of 33 pf to scl and sda inputs. sda 3302 family
semiconductor group 26 package outlines plastic-package, p-dip-18-5 (plastic dual in-line package) gpd05586 plastic-package, p-dso-20-1 (smd) (plastic dual small outline package) gps05094 sda 3302 family
semiconductor group 27 sda 3302 family sorts of packing package outlines for tubes, trays etc. are contained in our data book package information smd = surface mounted device dimensions in mm plastic-package, p-dso-16-1 (smd) (plastic dual small outline package) gps05119

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